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  LMH0036 www.ti.com snls254b ? march 2008 ? revised april 2013 LMH0036 sd sdi reclocker with 4:1 input multiplexer check for samples: LMH0036 1 features applications 2 ? supports smpte 259m (c) serial digital video ? sdtv serial digital video interfaces for: standard ? digital video routers and switchers ? supports 270 mbps serial data rate operation ? digital video processing and editing ? supports dvb-asi at 270 mbps equipment ? single 3.3v supply operation ? dvb-asi equipment ? 360 mw typical power consumption ? video standards and format converters ? integrated 4:1 multiplexed input description ? two differential, reclocked outputs the LMH0036 sd sdi reclocker with 4:1 input ? choice of second reclocked output or low- multiplexer retimes serial digital video data jitter, differential, data-rate clock output conforming to the smpte 259m (c) standard. the ? single 27 mhz external crystal or reference LMH0036 operates at the serial data rate of 270 mbps, and also supports dvb-asi operation at 270 clock input mbps. the LMH0036 includes an integrated 4:1 input ? lock detect indicator output multiplexer for selecting one of four input data ? output mute function for data and clock streams for retiming. ? auto/manual reclocker bypass the LMH0036 retimes the incoming data to suppress ? differential lvpecl compatible serial data accumulated jitter. the LMH0036 recovers the serial inputs and outputs data-rate clock and optionally provides it as an output. the LMH0036 has two differential serial data ? lvcmos control inputs and indicator outputs outputs; the second output may be selected as a low- ? 48-pin wqfn package jitter, data-rate clock output. controls and indicators ? industrial temperature range: -40 c to +85 c are: serial clock or second serial data output select, manual rate select input, sd indicator output, lock ? footprint compatible with the lmh0056 and detect output, auto/manual data bypass, and output lmh0356 mute. the serial data inputs, outputs, and serial data- rate clock outputs are differential lvpecl compatible. the cml serial data and serial data-rate clock outputs are suitable for driving 100 ? differentially terminated networks. the control logic inputs and outputs are lvcmos compatible. the LMH0036 is powered from a single 3.3v supply. power dissipation is typically 360 mw. the device is housed in a 48-pin wqfn package. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2008 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
LMH0036 snls254b ? march 2008 ? revised april 2013 www.ti.com typical application block diagram 2 submit documentation feedback copyright ? 2008 ? 2013, texas instruments incorporated product folder links: LMH0036 retimer/fifo vco/pll sdi0 lock detect sdo control logic auto bypass bypass/ o/p mute 50 50 xtal in/ext clk xtal out loop filter 1 loop filter 2 sco_en sco/sdo2 bypass sdi0 sdo 50 50 v cco v cco sco/sdo2 sdi1 sdi1 sdi2 sdi2 sdi3 sdi3 sel0sel1 sd lmh0074 equalizer crosspoint LMH0036 reclocker LMH0036 reclocker lmh0001 cable driver lmh0074 equalizer lmh0074 equalizer lmh0074 equalizer lmh0074 equalizer lmh0074 equalizer lmh0074 equalizer lmh0074 equalizer lmh0001 cable driver lmh0001 cable driver lmh0001 cable driver crosspoint crosspoint crosspoint
LMH0036 www.ti.com snls254b ? march 2008 ? revised april 2013 connection diagram the exposed die attach pad is the primary negative electrical terminal for this device. it must be connected to the negative power supply voltage. figure 1. 48-pin wqfn see package number rhs0048a copyright ? 2008 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: LMH0036 1 LMH0036 (top view) v cc sdi0 sdi0 sco/sdo2 sco/sdo2 v cc xtal in/ ext clk v ee v cc sdi1 sdi1 v cc sdi2 sdi2 sdi3 sdi3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 sdo sdo v ee v cc v ee lf1 sel1sel0 lf2 v ee sco_en v ee v cc v cc v ee v ee v cc v cc o/p mute xtal out v ee v ee v ee lock det v ee sd rsvd nc v ee v ee v ee bypass/ autobypass
LMH0036 snls254b ? march 2008 ? revised april 2013 www.ti.com pin descriptions pin name description 1 sdi0 data input 0 true. 2 sdi0 data input 0 complement. 4 sdi1 data input 1 true. 5 sdi1 data input 1 complement 7 sdi2 data input 2 true. 8 sdi2 data input 2 complement. 10 sdi3 data input 3 true. 11 sdi3 data input 3 complement. bypass/auto bypass mode select. bypasses reclocking when high. this pin has an internal 15 bypass/ auto bypass pulldown. data and clock output mute input. mutes the output when low. this pin has an internal 16 output mute pullup. 18 xtal in/ext clk crystal or external oscillator input. 22 xtal out crystal oscillator output. 24 lock detect pll lock detect output (active high). 28 sco/sdo2 serial clock or serial data output 2 complement. 29 sco/sdo2 serial clock or serial data output 2 true. 32 sdo data output complement. 33 sdo data output true. 36 sd sd indicator output. output is high when locked to 270 mbps. serial clock or serial data 2 output select. sets second output to output the clock when 37 sco_en high and the data when low. this pin has an internal pulldown. 43 lf1 loop filter. 44 lf2 loop filter. 45 nc no connect. not bonded internally. 46 rsvd reserved. do not connect or connect to ground. 47 sel0 data input select input. this pin has an internal pulldown. 48 sel1 data input select input. this pin has an internal pulldown. 3, 6, 12, 14, 30, 31, 34, 35 v cc positive power supply input. dap, 13, 17, 19, 20, 21, 23, 25, 26, 27, 38, 39, 40, 41, 42 v ee negative power supply input. these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 4 submit documentation feedback copyright ? 2008 ? 2013, texas instruments incorporated product folder links: LMH0036
LMH0036 www.ti.com snls254b ? march 2008 ? revised april 2013 absolute maximum ratings (1) (2) supply voltage (v cc ? v ee ) 4.0v logic supply voltage (vi) v ee ? 0.15v to v cc +0.15v logic input current (single input) vi = v ee ? 0.15v ? 5 ma vi = v cc +0.15v +5 ma logic output voltage (vo) v ee ? 0.15v to v cc +0.15v logic output source/sink current 8 ma serial data input voltage (v sdi ) v cc to v cc ? 2.0v serial data output sink current (i sdo ) 24 ma package thermal resistance ja 48-pin wqfn 26.1 c/w jc 48-pin wqfn 1.9 c/w storage temp. range ? 65 c to +150 c junction temperature +150 c lead temperature (soldering 4 sec) +260 c (pb-free) esd rating (hbm) 8 kv esd rating (mm) 400v esd rating (cdm) 1250v (1) ? absolute maximum ratings ? are those parameter values beyond which the life and operation of the device cannot be ensured. the stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. dc electrical characteristics and ac electrical characteristics specify acceptable device operating conditions. (2) it is anticipated that this device will not be offered in a military qualified version. if military/aerospace specified devices are required, please contact the texas instruments sales office/distributors for availability and specifications. recommended operating conditions supply voltage (v cc ? v ee ) 3.3v 5% logic input voltage v ee to v cc differential serial input voltage 800 mv 10% serial data or clock output sink current (i so ) 16 ma max. operating free air temperature (t a ) ? 40 c to +85 c dc electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified. (1) (2) symbol parameter conditions reference min typ max units v ih input voltage high level logic level inputs 2 v cc v v il input voltage low level v ee 0.8 v i ih input current high level v ih = v cc 47 65 a i il input current low level v il = v ee ? 18 ? 25 a v oh output voltage high level i oh = ? 2 ma all logic level 2 v outputs v ol output voltage low level i ol = +2 ma v ee + 0.6 v v sdid serial input voltage, sdi 200 1600 mv p-p differential v cmi input common mode v sdid = 200 mv sdi v ee +1.2 v cc ? 0.2 v voltage v sdod serial output voltage, 100 ? differential load sdo, sco 720 800 880 mv p-p differential v cmo output common mode 100 ? differential load sdo, sco v cc ? v voltage v sdod i cc power supply current, 270 mbps, ntsc color bar 109 ma 3.3v supply, total pattern (1) current flow into device pins is defined as positive. current flow out of device pins is defined as negative. all voltages are referenced to v ee (equal to zero volts). (2) typical values are stated for: v cc = +3.3v, t a = +25 c. copyright ? 2008 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: LMH0036
LMH0036 snls254b ? march 2008 ? revised april 2013 www.ti.com ac electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified. (1) symbol parameter conditions reference min typ max units br sd serial data rate smpte 259m (c) sdi, sdo 270 mbps tol jit serial input jitter 270 mbps (2) (3) (4) sdi > 6 ui p-p tolerance tol jit serial input jitter 270 mbps (2) (3) (5) sdi > 0.6 ui p-p tolerance t jit serial data output jitter 270 mbps (3) (6) sdo 0.02 0.08 ui p-p bw loop loop bandwidth 270 mbps, 300 khz < 0.1db peaking f co serial clock output 270 mbps data rate sco 270 mhz frequency t jit serial clock output jitter 2 3 ps rms serial clock output sdo, sco alignment with respect to 40 60 % data interval serial clock output duty sco 45 55 % cycle t acq acquisition time see (7) (8) 15 ms t r , t f input rise/fall time 10% ? 90% logic inputs 1.5 3 ns t r , t f input rise/fall time 20% ? 80% sdi 1500 ps t r , t f output rise/fall time 10% ? 90% logic outputs 1.5 3 ns t r , t f output rise/fall time 20% ? 80% (9) sco, sdo 90 130 ps f ref reference clock 27 mhz frequency f tol ref. clock freq. 50 ppm tolerance (1) typical values are stated for: v cc = +3.3v, t a = +25 c. (2) peak-to-peak amplitude with sinusoidal modulation per smpte rp 184-1996 paragraph 4.1. the test data signal shall be color bars. (3) this parameter is ensured by characterization over voltage and temperature limits. (4) refer to ? a1 ? in figure 1 of smpte rp 184-1996. (5) refer to ? a2 ? in figure 1 of smpte rp 184-1996. (6) serial data output jitter is total output jitter with 0.2ui p-p input jitter. (7) specification is ensured by design. (8) measured from first sdi transition until lock detect (ld) output goes high (true). (9) r l = 100 ? differential. 6 submit documentation feedback copyright ? 2008 ? 2013, texas instruments incorporated product folder links: LMH0036
LMH0036 www.ti.com snls254b ? march 2008 ? revised april 2013 device description the LMH0036 sd sdi reclocker with 4:1 input multiplexer is used in many types of digital video signal processing equipment. the LMH0036 supports the smpte 259m (c) standard, with a corresponding serial data rate of 270 mbps. dvb-asi data at 270 mbps may also be retimed. the LMH0036 retimes the serial data stream to suppress accumulated jitter. it provides two low-jitter, differential, serial data outputs. the second output may be selected to output either serial data or a low-jitter serial data-rate clock. controls and indicators are: serial data-rate clock or second serial data output select, manual rate select input, sd indicator output, lock detect output, auto/manual data bypass and output mute. serial data inputs are cml and lvpecl compatible. serial data and data-rate clock outputs are differential cml and produce lvpecl compatible levels. the output buffer design can drive ac or dc-coupled, terminated 100 ? differential loads. the differential output level is 800 mv p-p 10% into 100 ? ac or dc-coupled differential loads. logic inputs and outputs are lvcmos compatible. the device package is a 48 ? pin wqfn with an exposed die attach pad. the exposed die attach pad is electrically connected to device ground (v ee ) and is the primary negative electrical terminal for the device. this terminal must be connected to the negative power supply or circuit ground. serial data inputs, serial data and clock outputs serial data input and outputs the differential serial data inputs, sdi0-sdi3, accept 270 mbps serial digital video data. the serial data inputs are differential lvpecl compatible. these inputs are intended to be dc interfaced to devices such as the lmh0074 adaptive cable equalizer. these inputs are not internally terminated or biased. the inputs may be ac- coupled if a suitable input bias voltage is provided. the LMH0036 provides four independent, multiplexed data inputs. the active input channel is selected via the sel0 and sel1 pins, as shown in table 1 . figure 2 shows the equivalent input circuit for sdi[3:0] and sdi[3:0]. the LMH0036 has two, retimed, differential, serial data outputs, sdo and sco/sdo2. these outputs provide low jitter, differential, retimed data to devices such as the lmh0001 or lmh0002 cable driver. output sco/sdo2 is multiplexed and can provide either a second serial data output or a serial data-rate clock output. figure 3 shows the equivalent output circuit for sdo, sdo, sco/sdo2, and sco/sdo2. the sco_en input controls the operating mode for the sco/sdo2 output. when the sco_en input is high the sco/sdo2 output provides a serial data-rate clock. when sco_en is low, the sco/sdo2 output provides retimed serial data. both differential serial data outputs, sdo and sco/sdo2, are muted when the output mute input is a logic low level. sco/sdo2 also mutes when the bypass mode is activated when this output is operating as the serial clock output. when muted, sdo and sdo (or sdo2 and sdo2) will assume opposite differential output levels. the cml serial data outputs are differential lvpecl compatible. these outputs have internal 50 ? pull-ups and are suitable for driving ac or dc-coupled, 100 ? center-tapped, ac grounded or 100 ? un-center-tapped, differentially terminated networks. copyright ? 2008 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: LMH0036
LMH0036 snls254b ? march 2008 ? revised april 2013 www.ti.com figure 2. equivalent sdi input circuit (sdi[3:0], sdi[3:0]) figure 3. equivalent sdo output circuit (sdo, sdo, sco/sdo2, sco/sdo2) serial data clock/serial data 2 output the serial data clock/serial data 2 output is controlled by the sco_en input and provides either a second retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being processed. when operating as a serial clock output, the rising edge of the clock will be positioned within the corresponding serial data bit interval within 10% of the center of the data interval. differential output sco/sdo2 functions as the second serial data output when the sco_en input is a logic-low level. this output functions as the serial data-rate clock output when the sco_en input is a logic-high level. the sco_en input has an internal pull-down device and the default state of sco_en is low (serial data output 2 enabled). sco/sdo2 is muted when the output mute input is a logic low level. when the bypass mode is activated and this output is functioning as a serial clock output, the output will also be muted. if an unsupported data rate is used while in auto bypass mode with this output functioning as a serial clock output, the output is invalid. 8 submit documentation feedback copyright ? 2008 ? 2013, texas instruments incorporated product folder links: LMH0036 50 : sdo, sco/sdo2 v cc v cc 50 : v cc sdo, sco/sdo2 sdi[3:0] v cc v cc sdi[3:0] 2 k : 80 k : 1 pf 20 k : v cc 2 k :
LMH0036 www.ti.com snls254b ? march 2008 ? revised april 2013 control inputs and indicator outputs serial data input selector the serial data input selector (sel [1:0]) allows the user to select the active input channel. table 1 shows the input selected for a given state of sel [1:0]. table 1. data input select codes sel [1:0] code selected input 00 sdi0 01 sdi1 10 sdi2 11 sdi3 lock detect the lock detect (ld) output, when high, indicates that data is being received and the pll is locked. ld may be connected to the output mute input to mute the data and clock outputs when no data signal is being received. note that when the bypass/ auto bypass input is set high, lock detect will remain low. see table 2 . output mute the output mute input, when low, mutes the serial data and clock outputs. it may be connected to lock detect or externally driven to mute or un-mute the outputs. if output mute is connected to ld, then the data and clock outputs are muted when the pll is not locked. this function overrides the bypass function: see table 2 . output mute has an internal pull-up device to enable the output by default. bypass/ auto bypass the bypass/ auto bypass input, when high, forces the device to output the data without reclocking it. when this input is low, the device automatically bypasses the reclocking function when the device is in an unlocked condition or the detected data rate is a rate which the device does not support. note that when the bypass/ auto bypass input is set high, lock detect will remain low. see table 2 . bypass/ auto bypass has an internal pull- down device. table 2. control functionality lock detect output mute bypass/ auto bypass device status 0 1 x pll unlocked, reclocker bypassed 1 1 0 pll locked to supported data rate, reclocker not bypassed x 0 x outputs muted 0 lock detect x outputs muted 1 lock detect 0 pll locked to supported data rate, reclocker not bypassed sd the sd output indicates that the LMH0036 is locked and processing sd data rates. it may be used to control another device such as the lmh0002 cable driver. when this output is high it indicates that the data rate is 270 mbps. the sd output is a registered function and is only valid when the pll is locked and the lock detect output is high. the sd output is undefined for a short time after lock detect assertion or de-assertion due to a data change on the sdi input. see figure 4 for a timing diagram showing the relationship between sdi, lock detect, and sd. copyright ? 2008 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: LMH0036
LMH0036 snls254b ? march 2008 ? revised april 2013 www.ti.com figure 4. sdi, lock detect, and sd timing sco_en input sco_en enables the sco/sdo2 differential output to function either as a serial data-rate clock or second serial data output. sco/sdo2 functions as a serial data-rate clock when sco_en is high. this pin has an internal pull-down device. the default state (low) enables the sco/sdo2 output as a second serial data output. crystal or external clock reference the LMH0036 uses a 27 mhz crystal or external clock signal as a timing reference input. a 27 mhz parallel resonant crystal and load network may be connected to the xtal in/ext clk and xtal out pins. alternatively, a 27 mhz lvcmos compatible clock signal may be input to xtal in/ext clk. parameters for a suitable crystal are given in table 3 . table 3. crystal parameters parameter value frequency 27 mhz frequency stability 100 ppm @ recommended drive level operating mode fundamental mode, parallel resonant load capacitance 20 pf shunt capacitance 7 pf series resistance 40 ? max. recommended drive level 100 w maximum drive level 500 w operating temperature range ? 10 c to +60 c 10 submit documentation feedback copyright ? 2008 ? 2013, texas instruments incorporated product folder links: LMH0036 sdi 270 mbps data no data lock detect sd t 2 no data 270 mbps data no data t 2 t acq = acquisition time, defined in the ac electrical characteristics ta ble t 1 = time from lock detect assertion or deassertion until sd output is valid, typically 37ns (one 27 mhz clock period) t 2 = time from sdi input change until lock detect de-assertion, 1 ms maximum. sd output is not valid during this time. t acq t 1 t 1 t acq t 1 t 1
LMH0036 www.ti.com snls254b ? march 2008 ? revised april 2013 application information figure 5 shows a application circuit for the LMH0036. figure 5. application circuit bypass/ auto bypass has an internal pulldown to enable auto bypass mode by default. this pin may be pulled high to force the LMH0036 to bypass all data. output mute has an internal pullup to enable the outputs by default. this pin may be pulled low to mute the outputs. the xtal in/ext clk and xtal out pins are shown with a 27 mhz crystal and the proper loading. the crystal should match the parameters described in table 3 . alternately, a 27mhz lvcmos compatible clock signal may be input to xtal in/ext clk. the active high lock detect output provides an indication that proper data is being received and the pll is locked. the sd output may be used to drive the sd/ hd pin of an sdi cable driver (such as the lmh0002) in order to properly set the cable driver ? s edge rate for smpte compliance. it defaults to low when the LMH0036 is not locked. copyright ? 2008 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: LMH0036 LMH0036 sdi0 sdi0 12 3 4 5 6 7 8 9 10 11 12 sco_en 25 26 27 28 29 30 31 32 33 34 sco/sdo2 sco/sdo2 sdo sdo sd 13 14 15 16 17 18 19 20 21 22 v cc sdi1 sdi1 v cc sdi2 sdi2 sdi3 sdi3 v ee v cc v cc op mute xtal in bp/ auto-bp v ee v ee v ee v ee xtal out lock det 23 24 v ee v ee v ee v ee 35 36 v cc v cc v cc v cc 37 38 39 40 41 42 43 44 45 46 47 48 dap v ee v ee v ee v ee v ee sel1sel0 rsvd nc lf2 lf1 100 : differential data input 3 v cc 100 : differential data input 2 100 : differential data input 1 100 : differential data input 0 v cc 27 mhz 39 pf 39 pf data output clock output or 2 nd data output v cc 56 nf lock det op mute bp/ auto-bp sel1 sel0 sco_en sd v cc
LMH0036 snls254b ? march 2008 ? revised april 2013 www.ti.com sco_en has an internal pulldown to set the second output (sco/sdo2) to output data. this pin may be pulled high to set the second output as a serial clock. the external loop filter capacitor (between lf1 and lf2) should be 56 nf. this is the only supported value; the loop filter capacitor should not be changed. sel0 and sel1 have internal pulldowns to select the sdi0 input by default. the inputs are lvpecl compatible. the LMH0036 has a wide input common mode range and in most cases the input should be dc coupled. for dc coupling, the inputs must be kept within the common mode range specified in dc electrical characteristics . figure 6 shows an example of a dc coupled interface between the lmh0074 cable equalizer and the LMH0036. the lmh0074 output common mode voltage and voltage swing are within the range of the input common mode voltage and voltage swing of the LMH0036. all that is required is a 100 ? differential termination as shown. the resistor should be placed as close as possible to the LMH0036 input. if desired, this network may be terminated with two 50 ? resisters and a center tap capacitor to ground in place of the single 100 ? resistor. the outputs are lvpecl compatible. sdo is the primary data output and sco/sdo2 is a second output that may be set as the serial clock or a second data output. both outputs are always active. the LMH0036 output should be dc coupled to the input of the receiving device as long as the common mode ranges of both devices are compatible. figure 7 shows an example of a dc coupled interface between the LMH0036 and lmh0001 cable driver. all that is required is a 100 ? differential termination as shown. the resistor should be placed as close to the lmh0302 input as possible. if desired, this network may be terminated with two 50 ? resisters and a center tap capacitor to ground in place of the single 100 ? resistor. the LMH0036 has multiple ground connections, however; the primary ground connection is through the large exposed dap. the dap must be connected to ground for proper operation of the LMH0036. figure 6. dc input interface figure 7. dc output interface 12 submit documentation feedback copyright ? 2008 ? 2013, texas instruments incorporated product folder links: LMH0036 LMH0036 100 : sdo sdo 75 : lmh0001 sd sdi cable driver sdo sdi sdo sdi 75 : 75 : 75 : 75 : 75 : +3.3v coaxial cable coaxial cable 4.7 p f 4.7 p f 5.6 nh 5.6 nh sdo sdo LMH0036 sdi0 sdi0 lmh0074 sd sdi cable equalizer coaxial cable 75 : 37.4 : 75 : 6.8 nh 1.0 p f 1.0 p f sdi sdi 100 :
LMH0036 www.ti.com snls254b ? march 2008 ? revised april 2013 revision history changes from revision a (april 2013) to revision b page ? changed layout of national data sheet to ti format .......................................................................................................... 12 copyright ? 2008 ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: LMH0036
package option addendum www.ti.com 8-oct-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples LMH0036sqe/nopb active wqfn rhs 48 250 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 85 xl036 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 8-oct-2015 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant LMH0036sqe/nopb wqfn rhs 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 q1 package materials information www.ti.com 2-sep-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) LMH0036sqe/nopb wqfn rhs 48 250 213.0 191.0 55.0 package materials information www.ti.com 2-sep-2015 pack materials-page 2
mechanical da t a rhs0048a www .ti.com s q a 4 8 a ( r e v b )
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